Performance Bounds For The Conservative Parallel Discrete Event Simulation Of VLSI Circuits And Systems

Publication
Rawling, M., Francis, R. and Abramson, D. "Performance Bounds for the Conservative Parallel Discrete Event Simulation of VLSI Circuits and Systems", 15th Australian Computer Science Conference, Hobart, Jan 1992, pp 753 - 767.
Abstract
Parallel Discrete Event Simulation (PDES) is gaining popularity as a means of overcoming the design bottleneck traditionally suffered by commercial VLSI chip/circuit designers. There is much debate, however, as to the potential speedups available in such simulations and the best ways of achieving these speedups.

The two main approaches to PDES are the so-called conservative and optimistic strategies, of which the latter is generally thought to yield better potential speedups. However, optimistic simulation has potentially costly rollback requirements and in any event must be restricted to run conservatively in a non-functional environment such as that considered in this study. The deterministic nature of conservative simulation makes it possible to conduct an accurate trace-driven analysis of an existing sequential simulator in order to establish upper bounds on a conservative PDES implementation. This paper describes such an analysis carried out on a commercial VLSI digital circuit simulator. The results add to the current knowledge of the potential concurrency characteristics of such simulators and have been used to assess the viability of conservative PDES in this field.

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